Fairchild flyback converter

Flyback converters are widely employed in switched mode power supplies, including those for travel power adapters, chargers, computers, and other applications. Generally speaking, in a flyback converter, a power switch is closed to allow the primary winding of the transformer to receive an input voltage.

Closing the power switch increases the primary current and magnetic flux, stores energy in the transformer, and induces current on the secondary winding of the transformer. The induced current on the secondary winding has a polarity that places a diode rectifier in reverse bias to block charging of an output capacitor. When the power switch is opened, the primary current and magnetic flux drop, and the resulting induced current on the secondary winding changes polarity to thereby forward bias the diode rectifier and allow charging of the output capacitor to generate a DC output voltage.

A load is connected to receive the output voltage. A flyback converter may incorporate a clamp to reduce voltage and current stress on its switching components. An active clamp flyback converter is a flyback converter that has an active clamp. In one embodiment, an active clamp flyback converter includes a low-side switch that serves as a power switch and a high-side switch that serves as a clamp switch. The high-side switch can be operated in one of at least two active clamp switching modes, which is selected based on load condition.

In a complementary active clamp mode, the high-side switch is complementary turned on with the low-side switch, and the switching frequency of the low-side switch is decreased as the load increases and vice-versa. In a modified active clamp mode, the high-side switch is turned on twice in a same switching cycle, first by zero voltage switching ZVS and second by quasi-resonant switching QRS , and a QRS blanking time is increased as the load decreases and vice versa.

A ZVS delay time and a dead time between switching are adaptively set based on a duty cycle of the low-side switch.

The output voltage of the active clamp flyback converter is sensed from an auxiliary voltage of an auxiliary winding of the transformer. These and other features of the present invention will be readily apparent to persons of ordinary skill in the art upon reading the entirety of this disclosure, which includes the accompanying drawings and claims. In the present disclosure, numerous specific details are provided, such as examples of circuits, components, and methods, to provide a thorough understanding of embodiments of the invention.

Persons of ordinary skill in the art will recognize, however, that the invention can be practiced without one or more of the specific details. In other instances, well-known details are not shown or described to avoid obscuring aspects of the invention.

Generally speaking, the efficiency of an active clamp flyback converter is inherently limited by high root mean square RMS current in the clamp switch and the transformer.

The active clamp switching mode, i. The load condition may be detected from an output voltage feedback signal or from a signal that is derived from the integral of the drain-to-source current of the power switch, for example. The attenuation of the output voltage feedback signal may be changed depending on the active clamp switching mode.

In the example of FIG. For analysis purposes, FIG. In one embodiment the low-side switch S 1 comprises a metal oxide semiconductor field effect transistor MOSFET with a drain that is connected to a first end of the primary winding NP and a source that is connected to a first end of a current sense resistor RCS. The second end of the current sense resistor RCS is connected to ground.

On the secondary side, the converter includes a diode rectifier D 1 with an anode that is connected to a first end of the secondary winding NS and a cathode that is connected to a first end of an output capacitor CO. The second end of the output capacitor CO and the second end of the secondary winding NS are connected to ground. In one embodiment, the high-side switch S 2 comprises a MOSFET with a drain that is connected to a first end of the clamp capacitor C 2 and a source that is connected to the drain of the low-side switch S 1 and to the first end of the primary winding NP.

The second end of the clamp capacitor C 2 is connected to the second end of the primary winding NP. In one embodiment, the ACF controller is implemented as an integrated circuit IC with a package that includes an HG pin for driving the gate of the high-side switch S 2 , an LG pin for driving the gate of the low-side switch S 1 , a CS pin for receiving a current sense signal developed on the sense resistor RCS, an EC pin for programming the active clamp switching mode change point, a VS pin for receiving a voltage sense signal, a VDD pin for receiving a supply voltage, and an FB pin for receiving an output voltage feedback signal FIG.

The output voltage feedback signal is indicative of the output voltage VOUT, and may be generated using a conventional feedback circuit block not shown. The point at which the active clamp switching mode transitions from the first mode to the second mode, and vice versa, may be programmed by selecting the resistance of the resistor REC that is connected to the EC pin.

The voltage across R 2 is received by the controller as the sense voltage, from which output voltage conditions may be sensed for protection circuits, etc. The voltage across the resistor divider R 1 and R 2 is also employed to develop the supply voltage VDD across a capacitor C 3. In one embodiment, the controller controls the switching operation of the low-side switch S 1 and the high-side S 2 in accordance with one of two active clamp switching modes, namely a complementary active clamp mode and a modified active clamp mode.

Referring to the signals in complementary active clamp mode FIG. Accordingly, the low-side switch S 1 turns on once per switching cycle, i.

As its name implies, in complementary active clamp mode, the high-side switch S 2 is on when the low-side switch S 1 is off, and the high-side switch S 2 is off when the low-side switch S 1 is on. The high-side switch S 2 turns on once per switching cycle. When the high-side switch S 2 turns off, the low-side switch S 1 turns on after a dead time indicated by the turn-on dead-time signal. The magnetizing current increases when the low-side switch S 1 is on, and decreases when the low-side switch S 1 is off.

When the low-side switch S 1 is off, the current from the primary winding NP flows through the body diode of the high-side switch S 2 to charge the clamp capacitor C 2 see FIG. The high-side switch S 2 turns on after a dead time after the low-side switch S 1 turns off. In one embodiment, for improved efficiency, the switching frequency of the converter is automatically adjusted based on the load condition in complementary active clamp mode.

The switching frequency of the converter increases as the load decreases, and decreases as the load increases. The converter is preferably placed in complementary active clamp mode during heavy load conditions. Referring to the signals in modified active clamp mode FIG. The main difference being that in the modified active clamp mode, the high-side switch S 2 turns ON twice per switching cycle of the converter Accordingly, in one embodiment, the high-side gate drive signal to the high-side switch S 2 has two pulses per switching cycle.

When the low-side switch S 1 is turned off, the drain-to-source voltage of the low-side switch S 1 increases, with the first pulse FIG. The second pulse FIG. The pulse widths of the first and second pulses of the high-side gate drive signal may be preset or adaptively set. In some embodiments, the pulse width of the second pulse of the high-side gate drive signal is adaptively set based on the duty cycle of the converter In one embodiment, for improved efficiency, the QRS blanking time is automatically adjusted based on load condition.

The QRS blanking time may be increased i. The converter is preferably placed in modified active clamp mode during medium and light load conditions. As is well known, the load is heavy when the load draws a large amount of current from the converter, and the load is light when the load draws a small amount of current from the converter.

The QRS blanking time is a period during which turning on of the high-side switch S 2 by quasi-resonant switching is disabled. That is, the high-side switch S 2 cannot be turned on by quasi-resonant switching during the QRS blanking time. As explained, in the modified active clamp mode, the second pulse of the high-side gate drive signal is asserted by quasi-resonant switching. Generally speaking, quasi-resonant switching introduces lower conduction losses compared to complementary switching.

However, as the load decreases, the percentage of switching loss increases. Accordingly, for improved efficiency, the QRS blanking time is increased i. However, when the primary FET switches ON, a high turns ratio means less reverse voltage is applied across the secondary diode. Since the ON time is shorter, the discharge time of the secondary is longer so the current in the secondary diode is lower.

However, the reverse voltage across the secondary diode is higher. Having a turns ratio equal to something other than Vin:Vout is not necessarily a bad thing. Flyback Converter Design Procedure. We are now going to use a circuit similar to FIG 1, but this time to boost a voltage of 5V to 12V that can support a load of mA.

We are going to use the LTC, a fixed frequency kHz controller. Unlike with a boost converter where inductors are available in many different values, the perfect transformer turns ratio might be hard to come by. Therefore it is wise to start the design by choosing a transformer that is close to where we need to be and adjusting the components in the design to compensate for its shortcomings.

Many power supply books explain how to calculate the ideal transformer primary inductance and turns ratio, but most engineers do not have the luxury of a custom transformer service available. The turns ratio affects the peak primary current, peak secondary current and the duty cycle. In our example, if the turns ratio is too low less turns on the primary the duty cycle decreases and the primary current increases this is logical because if the MOSFET is on for a shorter duration, more current needs to be ramped in the primary per cycle.

If the turns ratio is too high the output voltage reflected back to the primary will be greater meaning a higher voltage MOSFET will be needed. In addition, the duty cycle will be longer the ON time of the MOSFET , so the OFF time the time when the secondary current is supplying the output capacitor will be shorter, so more secondary current needs to flow to furnish the load.

A primary to secondary turns ratio of approximately Vin:Vout is a good place to start. So with 5V input and 12V output a turns ratio of is a good choice. The circuit we are going to design will assume the secondary current ramps down to zero after which the primary MOSFET immediately switches back on again to begin charging the primary. In other words, the part is working on the boundary between continuous conduction mode where current is always flowing in either the primary or the secondary and discontinuous mode where there is a region of zero current in both windings before the MOSFET starts charging the primary again.

We will design for maximum load, therefore if the load current decreases, there will be a delay between the secondary current ramping down to zero and the primary current charging again discontinuous mode.

FIG 3 shows our outline architecture. FIG 3. Referring to FIG 2 earlier in the text, we see that the secondary current is triangular ramping down from a peak value to nearly zero. The area under this red waveform needs to have an average of mA to support our load. However, the secondary current is only present for a certain amount of time dictated by the duty cycle , so the current needs to be considerably greater than this.

A flyback converter has a duty cycle of. Earlier we calculated the duty cycle ignoring the diode drop. We can now include it without too much hardship.

If we include a diode drop of 0. Obviously the lower the output voltage, the more influential the diode drop is in our duty cycle equation.

Therefore to get the desired peak secondary current, we need to divide the peak mA current calculated above , by Thus the peak desired current in the secondary is.

For a more mathematical derivation of the above procedure, Click Here. A mA peak current in the secondary, with a turns ratio of means a peak primary current of 1. So we need to pick a transformer with a primary inductance of approximately 10uH, with a saturation current rating of at least 1.

This is quite a specific requirement and the reader will probably find it impossible to find a transformer with such characteristics. All is not lost however, as magnetics companies are now introducing general purpose transformers with 6 windings on one bobbin that can be configured in any way.

Since we have more current on the primary than secondary, it makes sense if our design has 3 windings in parallel for the primary and 3 windings in series for the secondary.

This ensures each of our 3 windings shares the 1. The Wurth is a suitable device. We must ensure that the transformer has a current rating of at least 1. If we exceed this current, the ferrite that the transformer is wound on will saturate and lose its magnetic properties. Thus the inductance value of the primary will collapse and from the equation. Now, parallel inductors wound on the same ferrite do not follow the same laws as separate inductors placed in parallel.

They keep the same overall inductance value, but share the current. This is explained the following Wurth document:. Transformer windings in series and parallel. Thus the has an inductance of As they share the current, the saturation current of 0. Rsense Choice. The current sense threshold on the LTC is 95mV, so a current sense resistor of 63mOhms ensures a peak current of 1. A current sense resistor of 50m Ohms should suffice. With an output voltage of 12V, the voltage on the secondary winding is Now, it is worth choosing a MOSFET with a drain source rating much higher than this since any transformer will not perfectly couple the primary energy into the secondary.

This term is called leakage inductance and can be modelled as an inductance in series with the primary that is not coupled to the secondary. Thus it stores energy that is not dumped into the secondary during the flyback cycle. This spike increases with primary current and if it is high enough, a snubber network may be required to reduce it.

The Qg of the MOSFET will also have an impact on the heat dissipation of the chip, especially if the input voltage to the chip is high. Charge is dictated by the equation:.

Since Frequency is the inverse of Time, we can write. So we can calculate the current needed to flow into the chip, just to charge the gate capacitance of the FET. The time ts is obtained fore, the voltage across Llk1 is Vsn-nVo. Very small Vsn results in a Vds severe loss in the snubber circuit, as shown in the above equation. Figure 2.

The snubber resistor with the proper rated power should be chosen based on the power loss. Therefore, the snub- ber capacitance is calculated using the above equation. When the converter is designed to operate in CCM, the peak drain current, together with the snubber capacitor voltage, decreases as the input voltage increases. The snubber capaci- tor voltage under maximum input voltage and full-load con- dition is obtained as follows: Figure 4.

The maximum voltage stress on the Ipeak2 is the primary peak current at the maximum input volt- internal SenseFET is around V, as shown in Figure 4. Figure 5 shows the reason. Steady-State Waveforms with 1nF Snubber transient period and steady-state period, respectively. Usually an ultra-fast diode with 1A current rating is used for the snubber circuit. Therefore, the snubber circuit should be redesigned. These are The power emission from Rsn is calculated as follows: around Figure 6.